Cmos image sensor and method for operating a cmos image sensor with increased dynamic range

ABSTRACT

There is disclosed a CMOS technology image sensor and a method for operating such an image sensor. This sensor includes a plurality of pixels ( 50 ) each including a photo-sensor element (PD) producing charge carriers in proportion to its illumination and storage means (C 1 ) capable of being coupled and uncoupled from the photo-sensor element at a determined instant in order to store, on a memory node (B) of the pixel, a measuring signal representative of the charge carriers produced by said photo-sensor element during an exposure phase.  
     Each pixel includes at least one MOS transistor (M 1 ; M 3 ) connected in series via its drain or source terminals to the photo-sensor element, and the transistor is configured such that it operates at least partially in weak inversion so that, during the exposure phase, the pixel has a logarithmic response for illumination levels higher than a determined illumination level.  
     This at least partially logarithmic response enables the pixel dynamic range to be increased.

[0001] The present invention generally concerns an integrated imagesensor and a method for operating such an integrated image sensor. Moreparticularly, the present invention concerns an integrated image sensorin CMOS technology with increased dynamic. Such CMOS image sensors areparticularly intended for making integrated photographic and videosdevices.

[0002] Owing to current integration technology, it is possible to makean operational image capturing device in integrated form. Such anintegrated image capturing device incorporates, on the same chip, aphoto-sensor component formed of a set of photo-sensor elementstypically organised in the form of a matrix, and a processing componentfor assuring the operations of capturing images and reading the datacaptured by the photo-sensor component.

[0003] Traditionally, integrated image capturing devices rely on chargetransfer techniques. According to these techniques, photo-generatedcharges are collected and transferred in a determined manner. The mostcommon charge transfer techniques use CCD (charge-coupled device)components or CID (charge injection device) components. Although thesedevices utilising these components have found numerous commercialapplications, they nonetheless have serious drawbacks. In particular,these components rely on non-standard manufacturing techniques, whichare, in particular, incompatible with standard CMOS manufacturingprocesses. Such components are thus obstacles, in terms of costs andmanufacturing ease, to the total integration of image sensors.

[0004] As a complement to the aforementioned techniques, a concept hasbeen developed around the use of p-n semiconductor junctions asphoto-sensor elements, these junctions being commonly calledphotodiodes. The essential advantage of such elements is their perfectcompatibility with standard CMOS manufacturing processes. Solutionsrelying on photodiodes as photo-sensor elements are known from the priorart, in particular from the document “A Random Access Photodiode Arrayfor Intelligent Image Capture” by Orly Yadid-Pecht, Ran Ginosar and YosiShacham Diamand, IEEE Transactions On Electron Devices, Vol. 38, no. 8,August 1991, pp. 1772-1780, incorporated by reference herein.

[0005] This document thus discloses an integrated image sensor in CMOStechnology in the form of a single chip. The architecture of the sensor,which is similar to that of RAM memories, is illustrated in FIG. 1. Thissensor, generally indicated by the reference numeral 1, includes amatrix 10 of pixels arranged in M lines and N columns. This matrix 10occupies most of the surface of the sensor. A particular pixel of matrix10 is read by addressing the corresponding line and column. For thispurpose the sensor further includes a line addressing circuit 20 coupledto the lines of matrix 10 and an output bus 30 coupled to the columns ofmatrix 10, both controlled by a control circuit 40.

[0006] Each pixel of matrix 10 has a structure conforming to theillustration of FIG. 2a. The pixel, indicated generally by the referencenumeral 50 in FIG. 2a, includes a photo-sensor element PD, a first stageA1, storage means C1 and a second stage A2, The photo-sensor element PDis formed of a reverse biased photodiode which typically operates bycollecting the electrons photo-generated during a so-called integrationperiod. First stage A1 is a sample and hold type circuit for sampling,at a determined time, the voltage value present across the terminals ofphotodiode PD. This sampled value is stored on storage means C1 which istypically formed of a capacitor. It will be noted that the voltage valuestored on capacitor C1 depends on the transfer function of first stageA1 and in particular on the ratio between the value of the capacitanceof photodiode PD and the capacitance of storage means C1. Second stageA2 enables the sampled voltage stored on storage means C1 to be read.The structure schematically described in FIG. 2a advantageously allowsseparation of the detection and reading processes.

[0007] The general structure of the pixel illustrated in FIG. 2a thusenables an electronic shutter function to be achieved, simultaneouslyallowing all the pixels of the sensor to be exposed and the signalrepresenting this exposure to be stored in each pixel, for subsequentreading. By means of this structure, one can thus make an image sensorcapable of taking snap-shots of a scene, i.e. a sensor perfectly suitedto capturing images of objects which are moving with respect to thesensor.

[0008] Various embodiments are envisaged and presented in theaforementioned prior art document. FIG. 2b shows, in particular, one ofthese embodiments wherein pixel 50 includes reverse biased photodiode PDand five n-MOS type transistors M1 to M5. Each pixel 50 includes amemory node, designated B, formed of a capacitor (capacitance C1) andprotected from the light, for example by a metal protective layer.

[0009] According to the aforementioned article, the pixel operates in anintegration mode and transistor M1 initialises photodiode PD at adetermined voltage before each integration period. Transistor M2 samplesthe charge accumulated by photodiode PD and stores the signal therebysampled at the memory node B. Transistor M2 also ensures isolation oruncoupling of photodiode PD and memory node B. Transistor M3initialises, in particular, memory node B at a determined voltage.Transistor M4 is a source follower transistor and transistor M5 is aline selection transistor and, during the read process, transfersvoltage from transistor M4 to an output bus common to all the pixels ina column. The signals applied to this structure include a high supplyvoltage V_(DD) and a low supply voltage V_(SS) forming ground, a firstinitialisation signal TI, a coupling signal SH, a second initialisationsignal RST, and a line selection signal RSEL.

[0010] A first terminal of photodiode PD is connected to ground V_(SS)and the other terminal is connected to the source terminals oftransistors M1 and M2 whose gate terminals are respectively controlledby signals TI and SH. The connection node between photodiode PD and thesource terminals of transistors M1 and M2 will be designated by thereference A in the following description. The drain terminals oftransistors M1, M3 and M4 are connected to the high supply voltage VDD.The second initialisation signal RST is applied to the gate terminal oftransistor M3. The source terminal of transistor M3, the drain terminalof transistor M2 and the gate terminal of transistor M4 are togetherconnected to memory node B of the pixel. The source terminal oftransistor M4 is connected, via line selection transistor M5, to theoutput bus common to all the pixels in a column. The line selectionsignal RSEL is applied to the gate terminal of transistor M5.

[0011] It will be noted that most of the CMOS image sensors adopt arolling shutter technique, i.e. exposure is effected line after line.Such non-simultaneous exposure inevitably leads to image distortion, inparticular when a moving image is captured.

[0012] The structure of the pixel illustrated in FIGS. 2a and 2 b istypically operated in accordance with an integration mode, i.e. thephoto-sensor elements are all first of all initialised at a determinedvoltage and then subjected to illumination during a determined period oftime, the charges produced by the photo-sensor elements beingaccumulated or integrated during this period. According to thisoperating mode, the pixel response can be termed linear. One drawback ofthis operating mode lies in the fact that the pixel dynamic range isreduced.

[0013] Numerous applications require wide dynamic range image sensors.In order to increase the dynamic range of an image sensor, using sensorsincluding pixels with a logarithmic type response is already known. FIG.3 shows a diagram of such a pixel arranged to have a logarithmicresponse. This pixel, globally indicated by the reference numeral 50,includes a reverse biased photodiode PD, and a first and second n-MOStype transistor Q1 and Q2. A first terminal of photodiode PD isconnected to ground V_(SS) and its other terminal is connected to thesource terminal of transistor Q1. The gate and drain terminals oftransistor Q1 are together connected to a supply potential VDD. In thisconfiguration, a low intensity current (of the order of fA to nA),generated by photodiode PD passes through transistor Q1, which isconnected as a resistor, and consequently operates in weak inversion orsubthreshold conduction. The voltage V_(OS) at the terminals ofphotodiode PD, at the connection node between photodiode PD andtransistor Q1, consequently has logarithmic dependence with respect tothe current generated via the effect of illumination. Transistor Q2forms a pixel read stage (similar to transistor M4 of FIG. 2b) and itsgate terminal is connected to the connection node between photodiode PDand transistor Q1.

[0014] The configuration illustrated in FIG. 3 is called a continuousconversion configuration, i.e. the voltage V_(OS), which is alogarithmic function of the current generated by photodiode PD, isdirectly converted and is representative of the pixel illumination.Unlike the linear response pixel structures, the charges produced by thephoto-sensor element are not “integrated” during a so-called integrationor period or exposure of determined duration.

[0015] One problem of the configuration illustrated in FIG. 3 lies inthe fact that the voltage variation produced as a function ofillumination tends to be relatively low (of the order of severalhundreds of mV). This makes the use of such a pixel difficult forimplementing a sensor with a high signal over noise ratio, in particularfor reduced illumination levels. Further, the response time of this typeof pixel becomes very long for low illuminations where thephoto-generated current is low.

[0016] Thus the document entitled “Wide-Dynamic-Range Pixel WithCombined Linear and Logarithmic Response and Increased Signal Swing”,Eric C. Fox et al., Sensors and Camera Systems for Scientific,Industrial and Digital Photography Applications, Proceedings of SPIEVol. 3965 (2000), pp. 4-10, has also proposed a pixel structure having acombined linear-logarithmic response. A diagram of this pixel is shownin FIG. 4.

[0017] Unlike the pixel of FIG. 3, this pixel further includes a thirdtransistor Q3 connected via its source terminal to the connection nodebetween photodiode PD and first transistor Q1 and, via its drainterminal, to a so-called initialisation or reset potential V_(BIAS). Theconduction state of transistor Q3 is controlled by the signal Φ_(RST)applied to its gate terminal. The initialisation potential V_(BIAS) ishigher than supply voltage V_(DD) so that when signal Φ_(RST) is at thehigh logic state, the voltage V_(OS) at the terminals of photodiode PDis brought to a voltage such that the gate-source voltage of transistorQ1 is less than the voltage necessary to allow subthreshold conductionof transistor Q1.

[0018] As soon as signal Φ_(RST) is returned to a low logic level,voltage V_(OS) decreases linearly via the effect of illumination untilthe gate-source voltage of transistor Q1 reaches a level such that thetransistor operates in weak inversion. Beyond this level, the pixelresponse becomes logarithmic in a similar way to that mentioned alreadywith reference to FIG. 3.

[0019] Like the structure illustrated in FIG. 3, the voltage V_(OS) atthe terminals of photodiode PD is directly applied to the input of theread stage. It is thus not possible to use these structures directly tomake an electronic shutter image sensor suitable for taking snap-shots.

[0020] One object of the present invention is thus to propose a methodfor operating an electronic shutter image sensor of the aforementionedtype having a pixel structure according to the illustrations of FIGS. 2aand 2 b with increased dynamic range.

[0021] In order to answer this object, the present invention concerns amethod for operating a CMOS image sensor the features of which arelisted in claim 1.

[0022] The present invention also concerns a CMOS image sensor whosefeatures are listed in the independent claim 15.

[0023] Advantageous embodiments of the present invention form thesubject of the dependent claims.

[0024] According to certain particular embodiments of the invention,there is thus proposed an image sensor and various methods for operatingsuch an electronic shutter image sensor such that each pixel has acombined linear-logarithmic response.

[0025] According to another particularly advantageous embodiment, thereis proposed an image sensor and a method for operating such anelectronic shutter image sensor such that each pixel has a combinedlinear-logarithmic response and increased sensitivity.

[0026] An advantage of the present invention lies in the fact that thedynamic range of such an electronic shutter image sensor, in particular,utilising a pixel structure like the structure illustrated in FIG. 2b,is increased.

[0027] Other features and advantages of the present invention willappear more clearly upon reading the following detailed description,made with reference to the annexed drawings, which are given by way ofnon-limiting example and in which:

[0028]FIG. 1, which has already been presented, illustratesschematically the conventional architecture of a CMOS image sensor;

[0029]FIGS. 2a and 2 b, which have already been presented, illustraterespectively a basic diagram and a detailed diagram of a known pixelstructure of the CMOS image sensor of FIG. 1;

[0030]FIG. 3, which has already been presented, shows a detailed diagramof a known logarithmic response pixel structure;

[0031]FIG. 4, which has already been presented, shows a detailed diagramof a known combined linear-logarithmic response pixel structure;

[0032]FIGS. 5a to 5 c shows diagrams illustrating first, second andthird variants of the method according to the invention for operatingthe structure of FIG. 2b such that it has, in addition to the electronicshutter function, a logarithmic type response;

[0033]FIGS. 6a and 6 b show diagrams illustrating fourth and fifthvariants of the method according to the invention for operating thestructure of FIG. 2b such that it has, in addition to the electronicshutter function, a combined linear-logarithmic response;

[0034]FIGS. 7a and 7 b illustrate first and second variants of the pixelstructure of FIG. 2b able to be operated such that they have a combinedlinear-logarithmic response;

[0035]FIGS. 8a and 8 b show diagrams illustrating sixth and seventhvariants of the method according to the invention respectively foroperating the pixel structures of FIGS. 7a and 7 b such that they have acombined linear-logarithmic response;

[0036]FIG. 9a shows a diagram illustrating an eighth particularlyadvantageous variant of the method according to the invention foroperating the structure of FIG. 2b such that it has, in addition to theelectronic shutter function, a combined linear-logarithmic response andincreased sensitivity; and

[0037]FIG. 9b shows the potential levels generated by the voltagesapplied to the gates of the transistors of the structure of FIG. 2boperated in accordance with the eighth variant illustrated in FIG. 9a.

[0038] Various variants of the method according to the invention foroperating pixel 50 of FIG. 2b such that it has a logarithmic responsefor illumination levels higher than a determined illumination level,will now be described with reference to the Figures.

[0039] It will be understood that the various variants of the methodaccording to the present invention are not limited to operating astructure like the structure illustrated in FIG. 2b, but can also beapplied in a similar manner to any type of structure which schematicallytakes the form of the structure of FIG. 2a, i.e. a structure including aphoto-sensor element and storage means capable of being coupled to thephoto-sensor element at a determined instant in order to produce andstore a measuring signal representative of the charge carriers producedby the photo-sensor elements during exposure, this structure having atleast one MOS transistor connected (directly or indirectly) via itsdrain or source terminal to the photo-sensor element. The structure ofFIG. 2b nonetheless constitutes a simple and particularly advantageousstructure. In this regard, it will be noted that transistor M1 ortransistor M3 can be configured to operate in weak inversion mode,transistor M1 being directly connected to photodiode PD whereastransistor M3 is connected to photodiode PD via coupling transistor M2.It will be seen that this possibility of using transistor M1 or M3independently assures great flexibility of use.

[0040]FIG. 5a thus shows a temporal diagram of the evolution of controlsignals TI, SH and RST applied respectively to transistors M1, M2 and M3of the pixel structure of FIG. 2b illustrating a first variant of themethod according to the invention. According to this first variant,transistor M1 is connected in a resistor configuration, the gateterminal of this transistor M1 being continuously connected to supplyvoltage V_(DD). The signal TI is thus kept at a voltage value applied tothe drain of transistor M1. According to this first variant, thecoupling signal SH is held at the high logic state so as to couplememory node B to the source terminal of transistor M1 (node A) duringexposure. The voltage present at memory node B is thus representative ofthe voltage present at node A at the terminals of photodiode PD. Thesignal RST applied to the gate of transistor M3 is held herecontinuously at a low logic level so as to make transistor M3non-conductive and thus uncouple memory node B from supply voltageV_(DD).

[0041] During exposure, the pixel thus behaves in a similar manner tothe structure illustrated in FIG. 3, i.e. transistor M1 behaves like ahigh impedance resistor through which the current generated byphotodiode PD passes. Since the generated current is of the order of fAto nA, transistor M1 operates in weak inversion mode the response of thepixel is thus also logarithmic.

[0042] Exposure is extended until the stage (instant t1) when the signalSH is brought to a low level thus uncoupling memory node B fromphotodiode PD, the measuring signal then being stored on storagecapacitor C1. The read operation can then be undertaken by means oftransistors M4 and M5. A new exposure phase begins by signal SH passingagain to its high level (instant t2).

[0043]FIG. 5b shows a temporal diagram of the evolution of controlsignals TI, SH and RST applied to the pixel structure of FIG. 2billustrating a second variant of the method according to the inventionfor operating the pixel such that it has a logarithmic response.According to this second variant, transistor M1 is also connected in aresistor configuration, the gate terminal of transistor M1 beingconnected to supply voltage V_(DD). Signal TI is thus held continuouslyat the voltage value applied to the drain of transistor M1. Couplingsignal SH is held here at the low logic state so as to uncouple memorynode B from the source terminal of transistor M1 (node A) duringexposure. As illustrated in the diagram of FIG. 5b, signal SH is brieflypulsed at the high logic state (instants t3 to t4) so as to sample andstore the measuring signal on memory node B. Before signal SH passes tothe high state, signal RST applied to transistor M3 is also brieflypulsed at the high logic state (instants t1 to t2) so as to initialisememory node B at a determined initialisation voltage.

[0044] Unlike the variant illustrated in FIG. 5a, the read operationaccording to this second variant can be undertaken in parallel to asubsequent exposure, as soon as the memory signal has been stored onmemory node B.

[0045]FIG. 5c shows a temporal diagram of the evolution of controlsignals TI, SH and RST applied to the pixel structure of FIG. 2billustrating a third variant of the method according to the inventionalso for operating the pixel such that it has a logarithmic response.According to this third variant, and unlike the preceding variants,transistor M3 is connected in a resistor configuration during exposure,the gate terminal of transistor M3 being connected to supply voltageV_(DD). Signal RST is thus kept, during the exposure phase, at thevoltage value applied to the drain of transistor M3. Coupling signal SHis kept at the high logic state so as to couple memory node B to thesource terminal of transistor M1 (node A) during exposure. Signal TI iskept at the low logic level during exposure.

[0046] The exposure is extended until instant t1 when coupling signal SHand signal RST are brought to a low level in order to isolate memorynode B and store the measuring signal on this node. Ideally, signals SHand RST should be simultaneously brought to the low level at instant t1.Given that the simultaneous switching of transistors M2 and M3 isdifficult to achieve in practice, signal RST will preferably be made topass first of all to the low level followed by signal SH. This wouldinduce a slight offset at the measuring signal present on memory node Bwhich could be considered and tolerated during reading.

[0047] Moreover, signal TI applied to the gate terminal of transistor M1should preferably be made to pass to a high level as soon as themeasuring signal has been stored on memory node B (instant t2 in FIG.5c). In fact, since photodiode PD is uncoupled, it continues to producecharge carriers which could disturb the signal present on memory node B.Operated in this way, transistor M1 thus allows the charge carriersproduced by photodiode PD to be drained.

[0048] From instant t2, the read operation can be undertaken by means oftransistors M4 and M5. At the end of the read operation, signal TI isreturned to its low level (instant t3) then signals SH and RST arereturned to the preceding levels for the next exposure.

[0049] The variants, which will now be presented with reference to FIGS.6a and 6 b, constitute advantageous variants enabling the structureillustrated in FIG. 2b to be operated such that it has a combinedlinear-logarithmic response.

[0050]FIG. 6a thus presents a fourth variant of the method according tothe present invention according to which transistor M1 is configuredsuch that it operates at least partially in weak inversion so that,during the exposure phase of the photo-sensor element, the pixel has alogarithmic response for illumination levels higher than a determinedillumination level.

[0051] As illustrated in the diagram of FIG. 6a, the signal TI appliedto the gate terminal of transistor M1 is switched between a first analoglevel, designated V₁, higher than supply voltage V_(DD) plus thethreshold voltage, designated V_(TH), of transistor M1, and a secondanalog level, designated V₂, lower than or equal to supply voltageV_(DD) but higher than threshold voltage V_(TH) of transistor M1. Thefirst analog level V₁ is applied during an initialisation phase forcingthe voltage at the terminals of photodiode PD to voltage V_(DD). Thesecond analog level V₂ is applied for a determined period ΔT (instantst1 to t5) during the exposure phase. According to this variant, pixelnodes A and B are uncoupled during the exposure phase (and during theinitialisation phase); signal SH being thus kept at a low logic level.This signal SH is briefly pulsed at a high level at the end of theexposure phase (instants t4 to t5) in order to sample and store themeasuring signal on memory node B. Before the passage of signal SH tothe high state, signal RST which is applied to transistor M3 is alsobriefly pulsed at the high logic state (instants t2 to t3) so as toinitialise memory node B at a determined initialisation voltage. Theread operation is undertaken in parallel with a subsequent exposure, assoon as the measuring signal has been stored on memory node B.

[0052] According to this fourth variant of the invention, as soon as thesignal TI is brought from its first to its second analog state (instantt1), photodiode PD is first of all released from its initialisationvoltage V_(DD). At this instant, the gate-source voltage of transistorM1 is such that the transistor is not conductive. The pixel response isthus of the linear type and voltage V_(OS) at the terminals ofphotodiode PD decreases linearly with a slope dependent upon the pixelillumination. If the illumination is such that voltage V_(OS) decreasesand becomes lower than the voltage applied to the gate terminal oftransistor M1, namely second analog level V₂ of signal TI, transistor M1enters weak inversion mode and the pixel response thus becomes of thelogarithmic type. In a way, a signal compression operation is performedon the pixel.

[0053]FIG. 6b shows a fifth variant of the method according to thepresent invention, similar to the variant illustrated in FIG. 6a butaccording to which transistor M3 is configured such that it operates atleast partially in weak inversion so that, during the photo-sensorexposure phase, the pixel has a logarithmic response for illuminationlevels higher than a determined illumination level.

[0054] As illustrated in the diagram of FIG. 6b, the two analog levelsV₁ and V₂ are applied to the gate terminal of transistor M3 respectivelyduring an initialisation phase and during an exposure phase for adetermined period of time Δt (instants t1 to t2). According to thisvariant, pixel nodes A and B are coupled during the exposure phase,signal SH being thus kept at a high logic level during this phase. Thissignal SH is brought to a low logic level (as is signal RST) at the endof the exposure phase (instants t2 to t5) in order to isolate memorynode B and to store the measuring signal on memory node B.

[0055] Moreover, signal TI applied to the gate terminal of transistor M1is preferably brought to a high level (at least higher than the voltageapplied to the gate of transistor M2) as soon as the measuring signalhas been stored on memory node B (instant t3 in FIG. 6b) allowingdrainage, via transistor M1, of the charge carriers produced byphotodiode PD.

[0056] From instant t3, the read operation can be undertaken by means oftransistors M4 and M5. At the end of the read operation, signal TI isreturned to its low level (instant t4) then signals SH and RST arereturned to the preceding levels for the next exposure as illustrated.

[0057] In a similar way to the variant of FIG. 6a, according to thisfifth variant of the invention, as soon as signal RST is brought fromits first to its second analog level (instant t1), photodiode PD isfirst of all released from its initialisation voltage substantiallyequal to V_(DD). At this instant, the gate-source voltage of transistorM3 is such that the transistor is not conductive. The pixel response isthus of the linear type and voltage V_(OS) at the terminals ofphotodiode PD decreases linearly with a slope dependent upon the pixelillumination, the voltage present on memory node B being representativeof voltage V_(OS) . If the illumination is such that the voltage atmemory node B decreases and becomes lower than the voltage applied tothe gate terminal of transistor M3, namely the second analog level V₂ ofsignal RST, transistor M3 enters a weak inversion mode and the pixelresponse then becomes of the logarithmic type, a signal compressionoperation is thus performed on the pixel.

[0058] A variant of the principles of FIGS. 6a and 6 b can consist innot switching the voltage applied to the gate terminal of transistor M1or M3, but in switching the voltage applied to the drain of saidtransistors. FIGS. 7a and 7 b thus illustrate first and second variantsof the pixel structure of FIG. 2b able to be operated such that theyhave a combined linear-logarithmic response.

[0059] The structure of FIG. 7a differs in particular from the structureof FIG. 2b in that the drain terminal of transistor M3 is connected to asupply potential V_(BIAS) higher than supply potential V_(DD). Thestructure of FIG. 7b differs from the structure of FIG. 2b in particularin that the drain terminal of transistor M1 is connected to supplypotential V_(BIAS).

[0060] The diagram of FIG. 8a illustrates the evolution of signals TI,SH and RST applied to the pixel structure of FIG. 7a. In a similar wayto the variant of FIG. 5a, transistor M1 is continuously connected in aresistor configuration, the gate terminal of this transistor M1 beingconnected to supply voltage V_(DD). During a first initialisation phase(until instant t1), signal RST is brought to its high logic level so asto apply a determined initialisation voltage higher than supply voltageV_(DD) to the source terminal of transistor M1. During thisinitialisation stage, and during the pixel exposure phase, signal SH isheld at a high logic level so as to couple pixel nodes A and B. Nodes Aand B are thus both initialised by means of transistor M3.

[0061] The exposure phase begins by the passage of signal RST to the lowlogic level (instant t1) and continues until the moment (instant t2)when signal SH is brought to a low logic level in order to insulatememory node B and thus store the measuring signal on memory node B.During this exposure step, the pixel has a linear response as a functionof the illumination and, as soon voltage V_(OS) at the terminals ofphotodiode PD becomes lower than the gate voltage of transistor M1(namely voltage V_(DD)), transistor M1 enters weak inversion mode andthe pixel then has a logarithmic response.

[0062] At instant t2, the measuring signal is thus stored on memory nodeB and the read process can then begin using transistors M4 and M5. Inthis case, the charge carriers produced by photodiode PD are drained viatransistor M1, voltage V_(OS) being held at its equilibrium leveldefined by the current generated by photodiode PD.

[0063] At the end of the read process (instant t3), signal SH isreturned to its preceding high logic level, followed (instant t4) byinitialisation signal RST. The whole process is then repeated for thenext acquisition.

[0064] The diagram of FIG. 8b illustrates the evolution of signals TI,SH and RST applied to the pixel structure of FIG. 7b. In a similar wayto the variant of FIG. 5c, transistor M3 is connected in a resistorconfiguration during the exposure phase, the gate terminal of transistorM3 being connected to supply voltage V_(DD). During a firstinitialisation phase (until instant t1), signal TI is brought to itshigh logic level so as to apply, to the source terminal of transistor M3(at memory node B), a determined initialisation voltage higher thansupply voltage V_(DD). During this initialisation step, signal SH iskept at a high logic level so as to couple nodes A and B. Nodes A and Bare thus both initialised by means of transistor M1.

[0065] The exposure phase begins by signal TI passing to the low logiclevel (instant t1) and continues until the moment (instant t2) whensignals SH and RST are brought to a low logic level in order to isolatememory node B and thus store the measuring signal on memory node B.During this exposure step, the pixel has a linear response as a functionof illumination and, as soon as the voltage of memory node B becomeslower than the gate voltage of transistor M3 (namely voltage V_(DD)),the transistor enters weak inversion mode and the pixel then has alogarithmic response.

[0066] At instant t2, the measuring signal is thus stored on memory nodeB and the read process can then begin using transistors M4 and M5.Preferably, as soon as the measuring signal is stored on memory node B,it is advantageous to return signal TI to the high logic level (instantt3) in order to drain the charge carriers, which are continuouslyproduced by photodiode PD via transistor M1.

[0067] At the end of the read process (instant t4), signals SH and RSTare returned to their preceding level and the whole process is repeatedfor the next acquisition.

[0068] A particularly advantageous variant of the method according tothe present invention will now be described with reference to FIGS. 9aand 9 b. In addition to the electronic shutter function and theincreased pixel dynamic range, this variant also allows the sensitivityof the pixel to be increased.

[0069] To a certain extent, this variant is similar to the variantillustrated in FIG. 6b, the only difference being that transistor M2 isno longer operated as a switch in order to couple and uncouple pixelnodes A and B. According to this variant, signal SH is brought,preferably continuously, to an intermediate logic level designatedV_(INT), i.e. a level located between the logic levels normally appliedto switch transistor M2. As will be seen in detail hereinafter, thisanalogue level V_(INT) is selected to be lower than analog level V₂applied to transistor M3 during exposure.

[0070] As regards the rest, signals TI and RST are operated in anessentially similar manner to the variant of FIG. 6b, as illustrated inthe diagram of FIG. 9a. In a first initialisation phase, signal RST isbrought to its first analog level V₁ higher than supply voltage V_(DD)plus threshold voltage V_(TH) of transistor M3, signal TI being kept atthe low logic state during this phase. Photodiode PD is initialised viatransistor M3 and transistor M2 at a voltage substantially equal to thegate voltage of transistor M2, i.e. V_(INT), less threshold voltageV_(TH) of transistor M2.

[0071] The exposure begins by signal RST passing (instant t1) to itssecond analog level V₂ less than or equal to supply voltage V_(DD) buthigher than threshold voltage V_(TH). During exposure, signal TI isalways kept at its low level. The charge carriers produced by photodiodePD are thus transferred entirely, during the exposure phase, to memorynode B, provided that the potential of memory node B has not reached thelevel of the potential barrier defined by transistor M2. Given thatthese charge carriers only “see” the capacitance of memory node B, theygenerate a more significant voltage variation. Via this mechanism, thepixel sensitivity is thus increased.

[0072] At instant t2, signal RST is brought to the low logic level inorder to uncouple the memory node B from supply voltage V_(DD) andsignal TI is simultaneously brought to a high logic level (at leasthigher than the gate voltage applied to transistor M2) in order tointerrupt the pixel exposure, or more exactly, the accumulation ofcharge carriers produced by photodiode PD. When signal TI is at the highlevel, the charge carriers produced by photodiode PD are drained viatransistor M1 and the measuring signal is stored on memory node B. In away, transistor M1 controlled by signal TI plays the role here ofshutter control similar to the function which was, until now, fulfilledby transistor M2.

[0073] It will be noted that one may perfectly well envisage switchingsignal SH applied to transistor M2 to a low logic level in order touncouple nodes A and B in accordance with the foregoing. However, asalready mentioned, it is preferable to switch transistor M1 so that thecharge carriers produced by photodiode PD are drained via thistransistor in order to avoid disturbing the measuring signal stored onmemory node B. According to the preferred variant illustrated, bycontrolling transistor M1 in this way, advantage is thereby taken of thepotential barrier generated by voltage V_(INT) applied to the gateterminal of transistor M2 to perform the uncoupling.

[0074] The read operation is undertaken as soon as signal TI is broughtto the high logic level and is followed by signal TI passing again toits low level again (instant t3) then (instant t4) signal RST passing toits first analog level V₁ again. The process is then repeated inaccordance with the chronology listed hereinbefore.

[0075]FIG. 9b illustrates schematically the level of the potentialsdefined by the voltages applied to the gate terminals of transistors M1,M2 and M3 during the initialisation, exposure and read phases.

[0076] Thus, during the initialisation phase (0<t<t1), nodes A and B arerespectively initialised at voltages substantially equal toV_(INT)−V_(TH) and V_(DD). During the exposure phase (t1<t<t2), thecharge carriers produced by photodiode PD at node A are entirelytransferred to memory node B and accumulate there. In a similar mannerto that previously described, the pixel response is first of all linearthen logarithmic if the illumination is such that the voltage of memorynode B decreases and becomes lower than the gate voltage of transistorM3, the latter then entering weak inversion mode. During the read phase(t2<t<t3), the charge carriers produced by photodiode PD are drained viatransistor M1 and the transfer of these charges to memory node B isinterrupted, the memory node being also uncoupled from supply voltageV_(DD) by transistor M3.

[0077] In the various variants which have been presented above, the readoperation can be achieved in accordance with a technique known to thoseskilled in the art as “Correlated Double Sampling” or CDS. According tothis known technique, the read operation of each line is broken downinto a first read phase of the voltage present on memory nodes B of thepixels in a line followed by a second read phase during which the memorynodes of the pixels in the line are reinitialised, normally by means oftransistor M3. A signal formed of the difference between the measuredsampled voltage and the initialisation voltage of the memory node isthen produced for each pixel. This technique allows fixed pattern noiseto be removed, i.e. the noise present at each pixel of the sensor whichis due to the slight differences in sensitivity which can exist betweenthe pixels. Both the line selection signal RSEL and the secondinitialisation signal RST are thus applied line by line during this readphase.

[0078] It should be noted that the variants presented utilise eithertransistor M1 or transistor M3 (designated the “first transistor” in theclaims) to generate an at least partially logarithmic response. Theother transistor, i.e. the transistor which is not operated in weakinversion mode, may not be necessary. Thus, the variant of FIG. 5a doesnot necessarily require the presence of transistor M3. Likewise,transistor M1 in the variants of FIGS. 5c and 6 b is not strictlynecessary. The present invention can thus be applied to any type ofpixel structure having a global architecture like that illustrated inFIG. 2a and which includes at least one transistor connected, directlyor indirectly, to the photo-sensor element, i.e. a transistor whosedrain terminal is connected to a determined voltage (for example supplyvoltage V_(DD)) and whose source terminal is connected either to node Aof the pixel (a first terminal of coupling transistor M2) or to node Bof the pixel (the second terminal of coupling transistor M2). The pixelstructure of FIG. 2b is however particularly advantageous since itoffers great flexibility of use as is apparent from the various variantspresented hereinbefore.

[0079] By way of improvement against the phenomenon of charge carrierdiffusion in the substrate, it is preferable to use n-well typephotodiodes i.e. photodiodes formed in n type wells. This structure hasthe advantage of forming a better obstacle to charge carrier diffusionthan a photodiode structure conventionally formed, for example of asimple n type diffusion region.

[0080] Numerous modifications and/or improvements to the presentinvention can be envisaged without departing from the scope of theinvention defined by the annexed claims. In particular, the pixelstructure used by way of example to illustrate the process according tothe present invention could in principle be achieved by means of acomplementary p-MOS technology or, if required, include additionaltransistors. It will be understood for example, that sampling transistorM2 essentially has the role of uncoupling the photodiode and the memorynode of the pixel and that other arrangements may be provided to fulfilthis function.

1.-20. (canceled).
 21. A method for operating a CMOS image sensorincluding a plurality of pixels, each of said pixels including aphoto-sensor element producing charge carriers in proportion to itsillumination and storage means capable of being coupled to and uncoupledfrom said photo-sensor element at a determined instant in order tostore, on a memory node of said pixel, a measuring signal representativeof said charge carriers produced by said photo-sensor element during anexposure phase, each pixel including a first MOS transistor comprisinggate, source and drain terminals, said first MOS transistor beingconnected in series via its drain and source terminals, on the one hand,to a supply voltage and, on the other hand, directly to saidphoto-sensor element, wherein said first MOS transistor is configuredsuch that it operates at least partially in weak inversion so that,during said exposure phase of said photo-sensor element, the pixel has alogarithmic response for illumination levels higher than a determinedillumination level which can be zero.
 22. The method according to claim21, wherein each pixel includes: a reverse biased photodiode formingsaid photo-sensor element; and coupling means including first and secondterminals for coupling and uncoupling said photodiode and said storagemeans, said photodiode being connected, on the one hand, to a firstsupply voltage and, on the other hand, to the first terminal of saidcoupling means and to the source terminal of said first transistor, thedrain terminal of said first transistor being connected to a secondsupply voltage, the second terminal of said coupling means beingconnected to said memory node of the storage means.
 23. The methodaccording to claim 22, wherein said first transistor is operated so thatsaid pixel has a logarithmic response, said method including thefollowing steps: a) an exposure step consisting in connecting said firsttransistor in a resistor configuration by connecting its gate terminalto said second supply voltage, said photodiode and said storage meansbeing coupled to each other by means of said coupling means; b) astorage step consisting in uncoupling said photodiode and said storagemeans, said measuring signal then being stored on said memory node; andc) a read step consisting in reading said measuring signal stored onsaid memory node.
 24. The method according to claim 22, wherein saidfirst transistor is operated so that said pixel has a logarithmicresponse, said method including the following steps: a) an exposure stepconsisting in connecting said first transistor in a resistorconfiguration by connecting its gate terminal to said second supplyvoltage, said photodiode and said storage means being uncoupled fromeach other by means of said coupling means; b) a storage step consistingin briefly coupling said photodiode and said storage means via saidcoupling means in order to store said measuring signal on said memorynode; and c) a read step consisting in reading said measuring signalstored on said memory node.
 25. The method according to claim 22,wherein said first transistor is operated so that said pixel has acombined linear-logarithmic response, said method including thefollowing steps: a) an initialisation step consisting in applying, tothe gate terminal of said first transistor, a voltage higher than saidsecond supply voltage plus the threshold voltage of said firsttransistor, said photodiode and said storage means being uncoupled viasaid coupling means; b) an exposure step of determined duration,consisting in applying to the gate terminal of said first transistor avoltage lower than or equal to said second supply voltage, but higherthan said first supply voltage plus the threshold voltage of said firsttransistor, said photodiode and said storage means being uncoupled; c) astorage step consisting in briefly coupling said photodiode and saidstorage means via said coupling means in order to store said measuringsignal on said memory node; and d) a read step consisting in readingsaid measuring signal stored on said memory node.
 26. The methodaccording to claim 24, wherein each pixel further includes a second MOStransistor including gate, source and drain terminals, the source anddrain terminals of this second transistor being respectively connectedto said memory node and to said second supply voltage, and wherein thestorage step is preceded by an initialisation step consisting ininitialising said memory node at a determined initialisation voltage viasaid second transistor.
 27. The method according to claim 25, whereineach pixel further includes a second MOS transistor including gate,source and drain terminals, the source and drain terminals of thissecond transistor being respectively connected to said memory node andto said second supply voltage, and wherein the storage step is precededby an initialisation step consisting in initialising said memory node ata determined initialisation voltage via said second transistor.
 28. Themethod according to claim 22, wherein said first transistor is operatedso that said pixel has a combined linear-logarithmic response, whereineach pixel further includes a second MOS transistor including gate,source and drain terminals, the source and drain terminals of thissecond transistor being respectively connected to said memory node andto a third supply voltage higher than said second supply voltage, andwherein the said first transistor is connected in a resistorconfiguration by connecting its gate terminal to said second supplyvoltage, the method including the following steps: a) an initialisationstep consisting in coupling said photodiode and said storage means viasaid coupling means and in making said second transistor conductive toinitialise the source terminal of said first transistor at a determinedinitialisation voltage higher than said second supply voltage; b) anexposure step of determined duration, consisting in making said secondtransistor non conductive at in keeping said photodiode and said storagemeans coupled; c) a storage step consisting in uncoupling saidphotodiode and said storage means and in keeping said second transistorin the non conductive state, said measuring signal then being stored onsaid memory node; and d) a read step consisting in reading saidmeasuring signal stored on said memory node.
 29. A method for operatinga CMOS image sensor including a plurality of pixels, each of said pixelsincluding a photo-sensor element producing charge carriers in proportionto its illumination and storage means capable of being coupled to anduncoupled from said photo-sensor element at a determined instant inorder to store, on a memory node of said pixel, a measuring signalrepresentative of said charge carriers produced by said photo-sensorelement during an exposure phase, each pixel including: coupling meansincluding first and second terminals for coupling and uncoupling saidphotodiode and said storage means; and a first MOS transistor comprisinggate, source and drain terminals, said first MOS transistor beingconnected in series via its drain and source terminals, on the one hand,to a supply voltage and, on the other hand, indirectly to saidphoto-sensor element via said coupling means, wherein said first MOStransistor is configured such that it operates at least partially inweak inversion so that, during said exposure phase of said photo-sensorelement, the pixel has a logarithmic response for illumination levelshigher than a determined illumination level which can be zero.
 30. Themethod according to claim 30, wherein each pixel includes: a reversebiased photodiode forming said photo-sensor element, said photodiodebeing connected, on the one hand, to a first supply voltage and, on theother hand, to the first terminal of said coupling means, the drainterminal of said first transistor being connected to a second supplyvoltage, the second terminal of said coupling means being connected tosaid memory node of the storage means and to the source terminal of saidfirst transistor.
 31. The method according to claim 30, wherein saidfirst transistor is operated so that said pixel has a logarithmicresponse, said method including the following steps: a) an exposure stepconsisting in connecting said first transistor in a resistorconfiguration by connecting its gate terminal to said second supplyvoltage, said photodiode and said storage means being coupled to eachother by means of said coupling means; b) a storage step consisting inuncoupling said photodiode and said storage means and applying a voltageto the gate terminal of the first transistor so that said transistor isnon-conductive, said measuring signal then being stored on said memorynode; and c) a read step consisting in reading said measuring signalstored on said memory node.
 32. The method according to claim 30,wherein said first transistor is operated so that said pixel has acombined linear-logarithmic response, said method including thefollowing steps: a) an initialisation step consisting in applying, tothe gate terminal of said first transistor, a voltage higher than saidsecond supply voltage plus the threshold voltage of said firsttransistor, said photodiode and said storage means being coupled to eachother via said coupling means; b) an exposure step of determinedduration, consisting in applying to the gate terminal of said firsttransistor a voltage lower than or equal to said second supply voltage,but higher than said first supply voltage plus the threshold voltage ofsaid first transistor, said photodiode and said storage means beingcoupled to each other; c) a storage step consisting in uncoupling saidphotodiode and said storage means and applying a voltage to the gateterminal of the first transistor so that said transistor isnon-conductive, said measuring signal being then stored on said memorynode; and d) a read step consisting in reading said measuring signalstored on said memory node.
 33. The method according to claim 32,wherein said coupling means is a MOS coupling transistor including gate,source and drain terminals, said source and drain terminals of thiscoupling transistor being respectively connected to said photodiode andsaid memory node, and wherein the gate terminal of said couplingtransistor is kept, at least during the initialisation step a) andexposure step b), at a lower voltage than the voltage applied to thegate terminal of said first transistor during the exposure step.
 34. Themethod according to claim 32, wherein each pixel further includes asecond MOS transistor including gate, source and drain terminals, thesource and drain terminals of said second transistor being respectivelyconnected to said photodiode and to said second supply voltage, andwherein during said read step, a voltage is applied to the gate terminalof the second transistor such that the charge carriers produced by saidphotodiode are drained via this second transistor.
 35. The methodaccording to claim 32, wherein each pixel further includes a second MOStransistor including gate, source and drain terminals, the source anddrain terminals of said second transistor being respectively connectedto said photodiode and to said second supply voltage, and wherein duringsaid read step, a voltage is applied to the gate terminal of the secondtransistor such that the charge carriers produced by said photodiode aredrained via this second transistor.
 36. The method according to claim33, wherein each pixel further includes a second MOS transistorincluding gate, source and drain terminals, the source and drainterminals of said second transistor being respectively connected to saidphotodiode and to said second supply voltage, and wherein during saidread step, a voltage is applied to the gate terminal of the secondtransistor such that the charge carriers produced by said photodiode aredrained via this second transistor.
 37. The method according to claim30, wherein said first transistor is operated so that said pixel has acombined linear-logarithmic response, wherein each pixel furtherincludes a second MOS transistor including gate, source and drainterminals, the source and drain terminals of said second transistorbeing respectively connected to said photodiode and to a third supplyvoltage higher than said second supply voltage, and wherein the saidfirst transistor is connected in a resistor configuration by connectingits gate terminal to said second supply voltage, the method includingthe following steps: a) an initialisation step consisting in couplingsaid photodiode and said storage means via said coupling means and inmaking said second transistor conductive to initialise the sourceterminal of said first transistor at a determined initialisation voltagehigher than said second supply voltage; b) an exposure step ofdetermined duration, consisting in making said second transistor nonconductive and in keeping said photodiode and said storage meanscoupled; c) a storage step consisting in uncoupling said photodiode andsaid storage means and in keeping said second transistor in the nonconductive state and in making said first transistor non-conductive,said measuring signal then being stored on said memory node; and d) aread step consisting in reading said measuring signal stored on saidmemory node.
 38. The method according to claim 22, wherein said couplingmeans is a MOS transistor including gate, source and drain terminals,said source and drain terminals of said transistor being respectivelyconnected to said photodiode and to said memory node.
 39. The methodaccording to claim 29, wherein said coupling means is a MOS transistorincluding gate, source and drain terminals, said source and drainterminals of said transistor being respectively connected to saidphotodiode and to said memory node.
 40. A CMOS image sensor including aplurality of pixels, each of said pixels including a photo-sensorelement producing charge carriers in proportion to its illumination andstorage means capable of being coupled to and uncoupled from saidphoto-sensor element at a determined instant in order to store, on saidstorage means, a measuring signal representative of said charge carriersproduced by said photo-sensor element during an exposure period, eachpixel including a first MOS transistor comprising gate, source and drainterminals, said first MOS transistor being connected in series via itsdrain and source terminals, on the one hand, to a supply voltage and, onthe other hand, directly to said photo-sensor element or indirectly tosaid photo-sensor element via coupling means, wherein said first MOStransistor is configured such that it operates at least partially inweak inversion so that, during said exposure phase of said photo-sensorelement, the pixel has a logarithmic response for illumination levelshigher than a determined illumination level which can be zero.
 41. Theimage sensor according to claim 40, wherein each pixel includes: areverse biased photodiode forming said photo-sensor element; andcoupling means including first and second terminals for coupling anduncoupling said photodiode and said storage means, said photodiode beingconnected, on the one hand, to a first supply voltage and, on the otherhand, to the first terminal of said coupling means, the drain terminalof said first transistor being connected to a second supply voltage, thesecond terminal of said coupling means being connected to said memorynode of the storage means, and the source terminal of said firsttransistor being connected to said first or second terminal of saidcoupling means.
 42. The image sensor according to claim 41, wherein saidsensor includes means for switching the gate voltage of said firsttransistor between first and second voltages respectively higher thansaid second supply voltage plus the threshold voltage of said firsttransistor and lower than or equal to said second supply voltage buthigher than said first supply voltage plus the threshold voltage of saidfirst transistor.
 43. The image sensor according to claim 41, whereineach pixel further includes a second MOS transistor including gate,source and drain terminals, the drain and source terminals of saidsecond transistor being respectively connected to said first or secondterminal of said coupling means and to a third supply voltage higherthan said second supply voltage, said second transistor forminginitialisation means for initialising the source terminal of said firsttransistor at a determined voltage higher than said second supplyvoltage.
 44. The image sensor according to claim 40, wherein thephotodiode is formed in an n-well and wherein said transistors are n-MOStransistors.
 45. The image sensor according to claim 40, wherein saidstorage means is formed of a capacitor protected from light by a metallayer.